clementyan 筆記分享: Digital Signal Processor 數位信號處理器簡介

Digital Signal Processor 數位信號處理器簡介

Real-Time operation、quickly
DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable.
Many DSP applications have constraints on latency.
Parallel Processing
SIMD 計算機組織
DMA 組合語言、計算機組織
Harvard architecture：(C620X/C670X)

物理上分開指令與資料的儲存記憶體與信號路徑。
The CPU can both read an instruction and perform a data memory access at the same time, even without a cache.So Harvard architecture computer can be faster,because instruction fetches and data access do not contend for a single memory pathway.
Instruction address zero is not the same as data address zero.Instruction address zero might identify a twenty-four bit value, while data address zero might indicate an eight bit byte that isn't part of that twenty-four bit value.
Remark:modified Harvard architecture

請參考：

以Texas Instruments為例，其晶片為TMS320族可分為下面幾類：

指令週期