Verilog FPGA Homework 多工器

Verilog FPGA Homework 多工器 4A037052_蘇偉諺

請使用verilog語法寫出2對1多工器，並測試出波形結果。

(一)

----------------- mux2_1.v -----------------

//mux.v

module mux2_1(a,b,s,y);

input a,b,s;

output y;

assign #0 y=s?b:a;

endmodule

-----------------------------------------------

---------------test_mux2_1.v--------------

// mux2_1.v的測試平台

`timescale 1ns/100ps

`include "mux.v"

module test_mux;

reg a,b,s;

wire y;

mux2_1 U1(a,b,s,y);//實體化

initial

begin

#0 a=0;b=0;s=1;

#10 b=1;

#10 a=1;b=0;s=0;

#10 b=1;

#10 a=0;b=0;

#10 $finish;

end

initial

begin

$dumpfile("testmux.vcd");

$dumpvars;

end

endmodule

//存為test_mux2_1.v

----------------------------------------------

-------------GTKWAVE 模擬波形圖--------------

(二)

----------------- mux3_1.v -----------------

//mux3_1.v

module mux3_1(a,b,c,s,t,y);

input a,b,c,s,t;

output y;

wire o;

assign #0 o=s?b:a;

assign #0 y=t?c:o;

endmodule

-----------------------------------------------

---------------test_mux3_1.v--------------

//mux3_1.v的測試平台

`timescale 1ns/100ps

`include "mux3_1.v"

module test_mux3_1;

reg a,b,c,s,t;

wire y;

mux3_1 U1(a,b,c,s,t,y);

initial

begin

#0 a=1;b=0;c=0;s=0;t=0;

#10 a=0;s=1;

#10 c=1;s=0;t=1;

#10 s=1;

#10 a=0;b=1;c=1;s=0;t=0;

#10 a=1;s=1;

#10 c=0;s=0;t=1;

#10 s=1;

#10 $finish;

end

initial

begin

$dumpfile("testMux3_1.vcd");

$dumpvars;

end

endmodule

//存為test_mux3_1.v

---------------------------------------

-------------GTKWAVE 模擬波形圖--------------