Digital Signal Processor 數位信號處理器 簡介

Digital Signal Processor 數位信號處理器 簡介

characteristics：

1. Real-Time operation、quickly
2. DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable.
3. Many DSP applications have constraints on latency.
4. Parallel Processing
5. SIMD 計算機組織
6. DMA  組合語言、計算機組織
7. Harvard architecture：(C620X/C670X)
• 物理上分開指令與資料的儲存記憶體與信號路徑。
• 
• The CPU can both read an instruction and perform a data memory access at the same time, even without a cache.So Harvard architecture computer can be faster,because instruction fetches and data access do not contend for a single memory pathway.
• Instruction address zero is not the same as data address zero.Instruction address zero might identify a twenty-four bit value, while data address zero might indicate an eight bit byte that isn't part of that twenty-four bit value.
• Remark:modified Harvard architecture
8. 從類比數位轉換器（ADC）獲得數據，最終輸出的是由數位類比轉換器（DAC）轉換為類比信號的數據。                 

DSP晶片:

請參考：

http://pemclab.cn.nctu.edu.tw/W3news/%E6%8A%80%E8%A1%93%E5%B0%88%E6%AC%84/TR-024.DSP%E6%95%B8%E4%BD%8D%E6%8E%A7%E5%88%B6%E5%99%A8%E7%B0%A1%E4%BB%8B/html/

以Texas Instruments為例，其晶片為TMS320族可分為下面幾類：

1. C1x、C2x、C5x、C6x為定點運算
2. C3x、C4x為浮點運算

參考資料：
http://en.wikipedia.org/wiki/Digital_signal_processor
http://zh.wikipedia.org/wiki/%E6%95%B8%E4%BD%8D%E8%A8%8A%E8%99%9F%E8%99%95%E7%90%86%E5%99%A8
http://140.134.32.129/scteach/scteach88/Tidsp/n17.htm
http://pemclab.cn.nctu.edu.tw/W3news/%E6%8A%80%E8%A1%93%E5%B0%88%E6%AC%84/TR-024.DSP%E6%95%B8%E4%BD%8D%E6%8E%A7%E5%88%B6%E5%99%A8%E7%B0%A1%E4%BB%8B/html/



IPS:Instructions per second

irregular不規則

instruction指令

architecture電腦內部結構

general-purpose通用

constantly經常

constraints強制

highly非常

implication意義

essential必要的

rely依靠

instruction sets指令集

term術語

http://www.hy1688.com.tw/SWITCH/DC%20JACK%20HOME/phone_jack.htm

指令週期