clementyan 筆記分享: Verilog Moore狀態機 Mealy狀態機 det010

1. 欲偵測位元串流輸入是否為”010”或”1001”，請寫出下列((A)~(C))方法之verilog程式。

(A) 不使用狀態機。

----------------------------------------det010_1001.v-------------------------------------------

module det010_1001(clk,rst,bitin,ok);

input clk,rst,bitin;

output ok;

assign ok=ok010|ok1001;

reg det0,det1,det01,det10,det100,ok010,ok1001;

always@(posedge clk or posedge rst)

if(rst) begin

det0 <= 0;

det1 <= 0;

det01 <= 0;

det10 <= 0;

det100 <= 0;

ok010 <= 0;

ok1001 <= 0;

end

else begin

det0 <= #1 ~bitin;

det01 <= #1 (det0&bitin)|ok1001;

ok010 <= #1 (det01&~bitin);

det1 <= #1 bitin;

det10 <= #1 (det1&~bitin)|ok010;

det100 <= #1 (det10&~bitin);

ok1001 <= #1 (det100&bitin);

end

endmodule

-------------------------------------GTKWAVE-----------------------------------------

(B) 使用Moore狀態機，請畫出狀態變遷圖後，再寫verilog程式碼。

-------------------------------------moore0101001.v-----------------------------------------

module moore(clk,rst,bitin,ok);

input clk,rst;

input bitin;

output ok;

parameter [2:0] s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7;

reg [2:0] state;

always@(posedge clk or posedge rst)

if(rst) state=s0;

else begin

case(state)

s0: if(bitin) state=s2;

else state=s1;

s1: if(bitin) state=s3;

s2: if(~bitin) state=s4;

s3: if(bitin) state=s2;

else state=s5;

s4: if(bitin) state=s3;

else state=s6;

s5: if(bitin) state=s3;

else state=s6;

s6: if(bitin) state=s7;

else state=s1;

s7: if(bitin) state=s2;

else state=s5;

endcase

end

reg ok;

always@(state)

case(state)

s7: ok=#1 1;

s5: ok=#1 1;

default: ok=#1 0;

endcase

endmodule

-------------------------------------GTKWAVE-----------------------------------------

---------------------------------------mealy.v-------------------------------------------

module meadly_010_1001(clk,rst,bitin,out);

input clk,rst;

input bitin;

output out;

parameter [2:0] s0=0,s1=1,s2=2,s3=3,s4=4,s5=5;

reg [2:0] state;

reg out;

always@(posedge clk or posedge rst)

if(rst) begin

state <= #1 s0;

out <= #1 1'b0;

end

else begin

out <= #1 0;

case(state)

s0: if(bitin) state <= #1 s2;

else state <= #1 s1;

s1: if(bitin) state <= #1 s3;

s2: if(~bitin) state <= #1 s4;

s3: if(bitin) state <= #1 s2;

else begin

state <= #1 s4;

out <= #1 1'b1;

end

s4: if(bitin) state <= #1 s3;

else state <= #1 s5;

s5: if(bitin) begin

state <= #1 s3;

out <= #1 1'b1;

end

else state <= #1 s1;

default: state <= #1 s0;

endcase

end

endmodule

-------------------------------------GTKWAVE-----------------------------------------

(D) 請討論Moore狀態機與Mealy狀態機之狀態變遷圖之關係。

Moore:狀態圖較多、較簡單，輸入決定狀態，狀態決定輸出，輸出指與狀態有關。

Mealy:狀態圖較少、較複雜，輸出會與輸入及狀態有關，即輸出由輸入與狀態共同決定。

2. (A)請設計一輸入位元串流為MSB(most significant bit)先之8位元串入並出移位暫存器，模組為sipo8(clk, rst, in, data_out[7:0])，其中clk為時脈，rst為重置訊號，in為串列位元輸入，data_out為8位元輸出。

-----------------------------------------sipo8 .v-------------------------------------------

module sipo8(clk,rst,in,data_out[7:0]);

input clk,rst;

input in;

output [7:0] data_out;

reg [7:0] data_out;

always@(posedge clk or posedge rst)

if(rst) data_out[7:0]=4'h0;

else data_out={data_out[6:0],in};

endmodule

-----------------------------------------GTKWAVE-------------------------------------------

(B)請設計一輸出位元串流為MSB(most significant bit)先之8位元並入串出移位暫存器，模組為piso8(clk, rst, load, data_in[7:0], out)，其中clk為時脈，rst為重置訊號，load為載入8位元data_in資料之控制訊號，out為串列輸出。

-----------------------------------------piso8.v-------------------------------------------

module piso8(clk,rst,load,data_in[7:0],out);

input clk,rst;

input load;

input [7:0] data_in;

output out;

reg [7:0] shift;

always@(posedge clk or posedge rst)

if(rst) shift=8'h0;

else if(load) shift=data_in;

else shift={shift[6:0],1'b0};

assign out=shift[7];

endmodule

-----------------------------------------GTKWAVE-------------------------------------------

3. 請設計一uart 8N1傳輸器，包率(bit per second)即為時脈，8N1表8位元資料，無同位元，1位停止位元，模組為uart8N1(clk, rst, load, txData[7:0], rx_in, tx_out, error, rxDone, rxData[7:0])，其中clk為時脈，rst為重置訊號，load為載入8位元txData資料之控制訊號，load由1變0時即開始傳送，tx_out為串列輸出，rx_in為串列輸入，當接收到停止位元=0時，error=1否則error=0，當接收到停止位元之後的第一個時脈rxDone=1，否則rxDone = 0，rxData為接收到之8位元資料，其傳輸時序圖如下：

-----------------------------------------uart.v-------------------------------------------

module uart8N1(clk,rst,load,txData[7:0],rx_in,tx_out,error,rxDone,rxData[7:0]);

input clk,rst,load,rx_in;

input [7:0] txData;

output tx_out,error,rxDone;

output [7:0] rxData;

//input [7:0] data;

//output tx;

parameter [1:0] s0=0,s1=1,s2=2,s3=3,s4=4;

reg [1:0] state,state1;

reg [3:0] index;

reg [7:0] data_reg,rxData;

reg tx_out,error,rx_in_1,rxDone,store;

always@(posedge clk or posedge rst or negedge load)

if(rst) begin

error<=0;

rxDone<=0;

rxData<=8'h0;

rx_in_1<=1'b0;

index<=4'h0;

data_reg<=8'h0;

tx_out<=1'b1;

state<=s0;

state1<=s0;

end

else if(!load) begin

rx_in_1=rx_in;

case(state)

s0: begin

data_reg<=txData;

state<=s1;

index<=4'h0;//可省？

tx_out<=1'b1;

end

s1: begin

tx_out=1'b0;//start位元

index<=4'h0;

state<=s2;

end

s2: begin

if(index < 4'h8) begin//piso

tx_out<=data_reg[0];

data_reg<={1'b0,data_reg[7:1]};

index<=index+1'b1;

if(index == 4'h7) begin

tx_out<=1'b1;

end

else state<=s0;

end

s3: begin

tx_out<=1'b1;//stop位元

state<=s0;

end

endcase

case(state1)

s0: if(~rx_in) state1 <= s1;

s1: begin

index <= 0; state1 <= s2;

rxData[7]<=rx_in_1;

end

s2: if(index < 4'h8) begin

rxData <= {rx_in_1,rxData[7:1]};

index <= index+1'b1;

if(index == 4'h7) begin

store<=~rx_in_1;

end

else begin

state1 <= s3;

rxDone<=1'b1;

error<=store;

end

s3: begin

error <=1'b0;

rxDone<=1'b0;

state1 <= s0;

end

endcase

end

endmodule

-----------------------------------------GTKWAVE-------------------------------------------

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2013年9月20日

Verilog Moore狀態機 Mealy狀態機 det010_1001 sipo8 piso8 uart

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